The present invention relates to a PLL circuit, and more specifically, to a PLL circuit suitable especially for suppressing a long term jitter.
FIG. 23 is a diagram showing a configuration of a classic PLL circuit. A PLL circuit 500 shown in FIG. 23 has a phase comparator 501, a charge pump 502, a filter 503, a VCO 504, and a frequency divider 507. The VCO 504 has a voltage-current conversion circuit 505 and an oscillator 506. The filter 503 has a resistance element Rpr, a capacitative element Cint, and a capacitative element Cpr. The phase comparator 501 detects a phase difference between a reference signal Ref and an output signal (feedback signal) FB of the frequency divider 507. The charge pump 502 sends a current Icp according to a detection result of the phase comparator 501. The filter 503 suppresses an alternating current component of the current Icp, and outputs a signal (voltage). The VCO 504 outputs an oscillating signal of a frequency according to the signal (voltage) from the filter 503. Specifically, in the VCO 504, the voltage-current conversion circuit 505 outputs a current Iro according to a signal (voltage) from the filter 503. The oscillator 506 outputs the oscillating signal of a frequency according to the current Iro. The frequency divider 507 divides a frequency of the oscillating signal from the VCO 504 by N (N: a natural number), and outputs it as the feedback signal FB.
Here, a transfer function Kop of an open loop of the PLL circuit 500 shown in FIG. 23 is expressed by the following Formula (1).
                    Kop        =                                            Kcco              ·              Icp              ·              gm                                      2              ⁢                                                π                  ⁢                  s                                2                            ⁢                              N                ·                Cint                                              ·                                    1              +                              sCint                ·                Rpr                                                    1              +                              sCpr                ·                Rpr                                                                        (        1        )            
Incidentally, Kcco represents a gain [rad/A] of the oscillator 506. Icp represents an output current value of the charge pump 502. gm represents a transconductance [A/V] of the voltage-current conversion circuit 505. s represents a Laplacian operator. N represents a frequency division ratio of the frequency divider 507. Cint represents a capacitance value of the capacitative element Cint. Rpr represents a resistance value of the resistance element Rpr. Cpr represents the capacitance value of the capacitative element Cpr.
FIG. 24 is a diagram showing an open loop gain of the PLL circuit 500. A band, a zero point, and a high order frequency are expressed from Formula (1) by the following Formula (2), Formula (3), and Formula (4), respectively.Frequency of band=Icp·Rpr·gm·Kcco/(2πN)  (2)Frequency of zero point=1/(Rpr−Cint)  (3)High order frequency=1/(Rpr−Cpr)  (4)
A frequency of the reference signal Ref, an oscillating frequency of the VCO 504, and a frequency division ratio N of the frequency divider 507 are determined by the specification. Once the oscillating frequency of the VCO 504 is determined by the specification, a transconductance gm of the voltage-current conversion circuit 505 and a gain Kcco of the oscillator 506 are determined according to it. Moreover, once the frequency of the reference signal Ref is determined by the specification, a required band is also determined according to it. Therefore, adjustment of the band needs to be performed by changing a value of the output current Icp of the charge pump 502 and the resistance value of the resistance element Rpr.
On the other hand, in order to make the oscillating signal of the PLL circuit be locked stably, it is necessary to decrease a frequency of the zero point sufficiently smaller than a frequency of the band. Generally, the frequency of the zero point needs to be decreased to be, for example, about 2.5 times smaller than the frequency of the band. Thus, once the band is determined, the zero point is also determined according to it. Since the zero point needs to be a fixed value or less, a product of the resistance value of the resistance element Rpr and the capacitance value of the capacitative element Cint needs to be more than or equal to a fixed value. However, since the resistance element Rpr becomes a noise source, there arises a necessity of reducing it to be less than or equal to a fixed value based on the long term jitter determined by the specification. Therefore, the capacitance value of the capacitative element Cint needs to be a magnitude more than or equal to a fixed value.
In short, the classic PLL circuit 500 shown in FIG. 23 had a problem that was not able to suppress the long term jitter within a range of the specification, without increasing a circuit scale.
A solution over such a problem is disclosed by U.S. Pat. No. 7,777,577. FIG. 25 is a diagram showing a configuration of a PLL circuit 600 disclosed by U.S. Pat. No. 7,777,577. FIG. 26 is a diagram showing a configuration of a loop filter 604 provided in the PLL circuit 600 shown in FIG. 25. The PLL circuit 600 shown in FIG. 25 has a phase comparator 601, two charge pumps 602,603, the loop filter 604, a voltage-controlled oscillator 605, and a frequency divider 606. The loop filter 604 has a gating circuit 607 and a filter 608, as shown in FIG. 26.
The gating circuit 607 is performing gating of an output current CPII of the charge pump 603 at a constant frequency. By changing the frequency of this gating, the amount of electric charges accumulated in a capacitative element 609 in the filter 608 is adjusted, and the frequency of the zero point is adjusted according to it. That is, in this PLL circuit 600, it is possible to adjust the frequency of the zero point only by changing a frequency of gating without increasing a capacitance value of the capacitative element 609. Therefore, for example, even when a resistance value of a resistance element 610 becomes small, it is possible to maintain the frequency of the zero point at a constant value by increasing the frequency of gating, without increasing the capacitance value of the capacitative element 609. That is, this PLL circuit 600 can suppress an output noise resulting from the resistance element 610 by making small a resistance value of the resistance element 610, without increasing the capacitance value of the capacitative element 609.
In addition to this, Japanese Unexamined Patent Publication No. S58 (1983)-107727 discloses a phase synchronizing circuit that has a voltage-controlled oscillator for generating an output signal of a frequency according to a control voltage, a first phase comparator for comparing an input signal and the output signal of the voltage-controlled oscillator, a low-pass filter for outputting a voltage according to a comparison result of the first phase comparator, a second phase comparator that compares the input signal and the output signal of the voltage-controlled oscillator and outputs a comparison result of a square wave characteristic, an integral circuit for integrating the comparison result of the second phase comparator, and an adder that adds the output of the low-pass filter and an output of the integral circuit and generates the control voltage (refer to FIG. 27).
Moreover, Japanese Unexamined Patent Publication No. Hei1 (1989)-258510 discloses a PLL circuit that has a phase comparator for detecting a phase difference between an input signal and an output clock signal, a proportional circuit for outputting a voltage V1 proportional to the phase difference detected by the phase comparator, an integral circuit for outputting a voltage V2 proportional to an integrated value of the phase difference detected by the phase comparator, and a voltage-controlled oscillator for generating the output clock of a frequency according to the voltages V1, V2 (refer to FIG. 28).